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ldp q0, q1, [x0] ldp q2, q3, [x0, 32] According to the ARM optimization guide for Cortex A72 (my target processor) each of these two instructions takes 6 cycles of execution time on the L-pipeline, for a total of 12 cycles. But I can also use a load with interleaving, which allows me to load all 4 registers at once:
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